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MAX4806, MAX4807, MAX4808*
Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers

Features Active-Clamp Circuitry to Reduce 2nd Harmonic Output

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    Description
    Request Full Data Sheet
    The MAX4806/MAX4807/MAX4808 integrated circuits generate high-voltage, high-frequency, unipolar or bipolar pulses from low-voltage logic inputs. These dual pulsers feature independent logic inputs, independent high-voltage pulser outputs with active clamps, and independent high-voltage supply inputs.

    The MAX4806/MAX4807/MAX4808 feature a 6Ω output impedance for the high-voltage outputs, and a 20Ω impedance for the active clamp. The high-voltage outputs are guaranteed to provide 2A of output current.

    All devices use three logic inputs per channel to control the positive and negative pulses and active clamp. Also included are two independant enable inputs. Disabling EN_ ensures the output MOSFETs are not accidentally turned on during fast power-supply ramping. This allows for faster ramp times and smaller delays between pulsing modes. A low-power shutdown mode reduces power consumption to less than 1µA. All digital inputs are CMOS compatible.

    The MAX4806 includes clamp output overvoltage protection, while the MAX4807 features both pulser output and clamp output overvoltage protection. The MAX4808 does not provide overvoltage protection (see the Ordering Information/Selector Guide in the full data sheet).

    The MAX4806/MAX4807/MAX4808 are available in a 56-pin (7mm x 7mm), TQFN exposed-pad package and are specified over the 0°C to +70°C commercial temperature range.

    Key Features   Applications/Uses
    • Highly Integrated, High-Voltage, High-Frequency Unipolar/Bipolar Pulser
    • 6Ω Output Impedance and 2A (min) Output Current
    • 20Ω Active Clamp
    • Pulser and Clamp Overvoltage Protection (MAX4806/MAX4807)
    • 0 to +220V Unipolar or ±110V Bipolar Outputs
    • Matched Rise/Fall Times and Matched Propagation Delays
    • CMOS-Compatible Logic Inputs
    • 56-Pin, 7mm x 7mm, TQFN Package

     
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    Document Ref.: 19-4366; Rev 0; 2008-11-29
    This page last modified: 2008-11-29



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